An Inter-Integrated Circuit bus (I2C-bus) is a serial bus that is often used to attach low-speed peripherals within or to a motherboard, embedded system, or cellphone. As shown in FIG. 1, an I2C-bus 101 includes only two bi-directional bus lines, which include a serial data line (SDA) and a serial clock line (SCL). As also shown in FIG. 1, a pull-up resistor (Rp) is connected between each bus line and a supply voltage rail (VDD). Typical voltages used for VDD are +5 V or +3.3 V, although systems with other (e.g., higher or lower) supply voltage rail voltages are permitted. The pull-up resistors (Rp) pull both the SDA and SCL lines HIGH when the bus is free. In FIG. 1, one master device 102 (e.g., a microcontroller) and three slave devices 104 (individually labeled 104a, 104b and 104c) are shown as being connected to the I2C-bus 101.
Electronic systems increasingly use integrated circuits (ICs) interconnected by an I2C-bus. Such ICs, because of their compatibility with the I2C-bus, are often referred to as I2C compatible chips, or more generally, I2C compatible devices. Exemplary I2C compatible devices include, but are not limited to, microcontrollers, liquid crystal displays (LCDs), LED drivers, input/output ports, random access memory (RAM), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors and digital signal processors (DSPs). The output stages of such I2C compatible devices, which are open-drain or open-collector, can be used to selectively pull down the SDA and SCL lines, to thereby provide data and clock signals.
There are four potential modes of operation for a given I2C compatible device, although most devices only use a single role (master or slave) and its two modes (transmit and receive). These modes include: master transmit—master device is sending data to a slave; master receive—master device is receiving data from a slave; slave transmit—slave device is sending data to a master; and slave receive—slave device is receiving data from the master.
The master is initially in master transmit mode by sending a start bit followed by the 7-bit address (which can be referred to as an I2C address) of the slave it wishes to communicate with, which is followed by a single read/write bit representing whether it wishes to read from (1) or write to (0) the slave. The start bit informs all of the ICs connected to the bus to listen to the bus for an incoming address. When each IC receives the address, the IC will compare it with its own address. If the received address doesn't match the IC's address, then the IC knows it is not being addressed. If the received address matches the IC's address, then the IC knows it is being addressed, in response to which the IC produces an acknowledgement (ACK) bit (active low for acknowledged). In other words, if the addressed slave exists on the bus, then it will respond with an ACK bit for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. If the master device wishes to write to the slave device then it repeatedly sends a byte with the slave sending an ACK bit (in this situation, the master is in master transmit mode and the slave is in slave receive mode). If the master device wishes to read from the slave device then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one (in this situation, the master is in master receive mode and the slave is in slave transmit mode). The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a “combined message”).
For the purpose of this description, the bits transmitted by a master, which includes a start bit followed by a 7-bit address, followed by a read/write bit, can be referred to as a read command or a write command, depending on the read/write bit.
Because only 7 bits can be used to designate the address of the slave, there are only 2^7 (i.e., 128) possible addresses. However, since 16 addresses are reserved, conventionally a maximum of 112 different devices can be address (i.e., 128−16=112).
In some cases, multiple applications of the same IC are desired, which means many of the same ICs (e.g., multiple instances of the same peripheral IC) may be attached to the same I2C-bus. However, because each device must have a unique I2C address, using multiple ICs with the same I2C address can result in data corruption. The most common solution to this potential problem is to design peripheral I2C-compatible devices with several selectable addresses. For example, an I2C compatible device may include two pins that are dedicated to selecting the address of the device, and thus, that enables the device to be assigned one of four different addresses. However, if the number of identical devices exceeds the number of selectable addresses (four, in this example), the same address overlap problem exists. From a cost and space perspective, it would not be practical to simply keep adding more pins that are dedicated to selecting the address of the device.
There are hundreds of different I2C compatible devices that are currently being manufactured. While some may be designed to have several selectable addresses, other are designed with a fixed address. Because only 112 different device addresses are available, it is quite likely that two different ICs that provide completely different functionality can have the same address and be attached to the same I2C-bus. This can prevent such two ICs from being separately addressable, since each device must have a unique I2C address. If two different ICs have the same address and are connected to the same I2C-bus, this also can result in data corruption.
There are presently no convenient solutions to the above described I2C addressing limitations. The most common solution is to create another independent I2C-bus with another full set of addresses, but this requires another I2C port on the master controller, which is undesirable.